CIS-77 Home http://www.c-jump.com/CIS77/CIS77syllabus.htm
Simplified x86 data path :
The size of input quantities of ALU is often referred to as word length of the computer.
Many processors today have word length of 32 and 64 bit.
Processing unit also includes a set of registers for temporary storage of data and memory addressing.
The size of quantities processed by ALU is the word length of the computer.
The word length does not affect what a computer can compute.
A computer with a smaller word length can do the same computation as one with a larger word length...
...but it will take more time.
For example, to add two 64 bit numbers,
word length = 16 takes 4 adds. word length = 32 takes 2 adds. word length = 64 takes 1 add.
I/O controller provides the necessary interface to I/O devices.
Takes care of low-level, device-dependent details.
Provides necessary electrical signal interface.
Processor and I/O interface points for exchanging data are called I/O ports.
Two ways of mapping I/O ports:
I/O ports are mapped to the memory address space.
Reading/writing I/O is similar to reading/writing memory.
Can use memory read/write instructions.
Motorola 68000 uses memory-mapped I/O.
Separate I/O address space.
Intel 80x86 processors support isolated I/O.
Requires special I/O instructions, like IN and OUT on x86.
Pentium x86 provides 64 KB of I/O address space.
Can be used for 8-, 16-, and 32-bit I/O ports.
Combination cannot exceed the total I/O address space, can have either
64 K 8-bit ports
32 K 16-bit ports
16 K 32-bit ports
A combination of these for a total of 64 KB.
I/O instructions do not go through memory segmentation or paging.
I/O address refers to the physical I/O address.
Central idea of von Neumann model is that both program and data stored in computer memory:
Program is a sequence of instructions
Instruction is a binary encoding of operations and operands:
For example, an arithmetic expression
-a + b * c
could be computed by a program with three machine instructions
neg ax ; negate (multiply by -1) imul bx, cx ; multiply and store result in bx add ax, bx ; add and store result in ax
where NEG, IMUL, ADD are arithemtic instructions, AX, BX, and CX are operands.
Instructions are most basic units of processing.
Instructions are executed under control of the control unit.
The x86 Intel CPU family is generally classified as a Von Neumann Architecture Machine.
Most pervasive ISA in the marketplace.
Opcodes have zero or more operands.
Instructions and operands have strong support for data types.
All x86 Assemblers are free, including Microsoft Macro Assembler,
Fullscreen 32-bit debuggers WinDbg, OllyDbg, and MS Visual Studio.
Instruction set architecture (ISA) is an important design issue for CPU designers:
caches, pipelining, superscalar implementation can be added to the design later, but
it is very difficult to change the CPU instructions once in production and people writing software...
...LOOP instruction on the x86 CPU sees very little use in modern high-performance programs.
Expandability is a big concern (predicting future needs.)
Legacy support is almost the opposite of expandability.
Each instruction requires some number of transistors on the CPU's silicon die.
Design a simple instruction set to begin with and leave room for later expansion -
main reason the x86 is so popular and long-lived.
Intel started with a relatively simple CPU and figured out how to extend the instruction set to accommodate new features.
IBM decided that open documentation is a good thing.
IBM published the
Intel introduced microprocessors in 1969: 4-bit microprocessor 4004.
8-bit microprocessors are 8080 and 8085 models.
8086 introduced in 1979.
20-bit address bus, 16-bit data bus.
(8088 is a less expensive version.)
Uses 8-bit data bus.
Can address up to 4 segments of 64 KB.
Referred to as the real mode addressing.
Still fully compatible with modern x86 chips.
A faster version of 8086.
16-bit data bus and 20-bit address bus.
Improved instruction set.
Introduced protected mode addressing.
Enhanced with memory protection capabilities with some instructions to control protected mode.
24-bit address bus.
16 MB address space.
Segmentation in protected mode is different from the real mode.
Allows the operating system to run multiple processes at the same time.
The 80286 was the minimum for running Windows 3.1 and higher.
The 80386 and many of its successors are 32-bit CPUs.
Internal registers are 32 bits in size.
Unlike its predecessors, the 80386 processor can handle both 16-bit and 32-bit data.
Supports entire instruction set of 80286.
Adds several new instructions as well.
Software written for the 80286 runs unchanged on the 80386, but the chip is faster.
The 80386 implements many new hardware-level features, including
segmentation can be turned off (flat model).
support for multiple virtual 8086 processes.
addressing of up to 4 gigabytes of memory.
specialized debugging registers.
32bit operating systems such as Windows NT required 80386 or higher processor.
More embedded systems nowdays use the 80386 CPU.
high speed data communications devices.
tra-high-speed data acquisition gear.
Cockpit displays of some modern jetliners use 80386 as controllers.
The 80486 processor is an enhanced version of the 80386 with
instruction pipelining allows parallel execution capability to instruction decode and execution units.
executes many instructions 2-3 times faster.
achieves scalar execution of 1 instruction per clock cycle.
The chip incorporates
math coprocessor for performing floating-point arithmetic
8 Kilobyte memory cache.
(The math coprocessor was disabled on a variation of the chip called the 80486SX.)
Fully compatible with 80386 software.
Later versions introduced energy savings for laptops.
Pentium was introduced in 1993, followed by
Pentium Pro in 1995,
Pentium II in 1997,
Pentium III in 1999,
Pentium IV 2001.
Similar to 80486 but with 64-bit data bus.
Wider internal datapaths: 128- and 256-bit wide.
Added second execution pipeline.
Superscalar performance allows two instructions per clock cycle.
Doubled on-chip level-1 cache:
one 8 KB for data
another 8 KB for instructions.
Added branch prediction.
Introduced in 1995.
Three-way superscalar performance, 3 instructions per clock cycle.
36-bit address bus.
64 GB address space.
Introduced dynamic execution:
In addition to the level-1 cache, has 256 KB level-2 cache.
Introduced in 1997.
Added multimedia (MMX) instructions.
Doubled on-chip level-1 cache:
16 KB for data
16 KB for instructions.
Introduced comprehensive power management features:
In addition to the level-1 cache has 256 KB level-2 cache.
(All previous x86 designs were CISC.)
Uses 64-bit address bus
128-bit data bus
Introduced several advanced features:
Predication to eliminate branches