### 1. Sequential Logic Circuits

 Muxes, decoders, and full adders are combinational logic circuits. Combinational logic circuits have no capacity of storing information. A different type, called sequential logic circuit, can, in addition to combinational logic, remember values and also base decisions on both input values and stored values. Sequential logic circuit: •

### 2. Sequential Logic Circuits and FSM

 Sequential logic circuits are building blocks of finite state machines. Finite state machines are widely used. For example, street traffic light controller device is FSM setting traffic lights to RGB values, depending on the combination of current light setting, and input from optical sensors on the road. Sequential logic circuit: •

### 3. System State The state of a system is a snapshot of all elements at the moment when the snapshot is taken. For example, the progress of tic-tac-toe game can be described by snapshots of the board after each player's move.
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### 4. Finite State Machine, the FSM

• A combination of states presents a system behavior.

• An FSM consists of five elements:

1. finite number of states

2. finite number of external inputs

3. finite number of external outputs

4. specification of all possible state transitions

5. specification of what determines each external output value.

• Each transition describes what it takes to get from one state to another.

### 5. The State Diagram

 An FSM can be conveniently represented by means of the state diagram. The states are represented by state symbols (rectangles with rounded corners or circles.) The transitions are represented by arrows connecting the state symbols. The state machine may be used as a protocol specification, showing the legal order of operations. Phone call state UML diagram: •

### 6. The State Diagram Example

 The output is 101 when system state is X. The output is 110 when system state is Y. The output is 001 when system state is Z. •

### 7. The Clock

 How transitions from state to state are triggered? A clock circuit is a mechanism that triggers FSM state transitions. In digital logic terms, clock is a signal that alternates between 0 and 1. The above picture shows repeated sequence of 3 signals, called clock cycles, or intervals. In digital logic circuits, the transition from one FSM state to another occurs at the start of each clock cycle. Clock cycle includes both 1 and 0 signals: 1 triggers transition, 0 allows to update internal information associated with the new state.
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### 8. Traffic Danger Sign

 Consider traffic danger sign: •

### 9. Danger Sign FSM The purpose of FSM is to enable the lights to flash. The FSM has one external switch: on/off. Signals are visible on the diagram as 1 and 0 next to each state transition arrow. Traffic danger sign FSM: •

### 10. Complete FSM example

 The traffic danger sign can be in one of four states. If external input is 0, we immediately transition to state named all off and remain in that state until external input changes back to 1. If external input is 1, the lights should flash. •

### 11. Complete FSM example, Cont.

 Light flash is implemented as external outputs unique to each state. The FSM relies on two bits of memory to keep track of the lights behavior. Thus, the FSM states are identified by four possible combinations of those two bits. •

### 12. Combinational Logic Circuit

• Implementation of the traffic sign logic is based on the programmable logic array, discussed earlier.

• The logic circuit is driven by the inputs from the external switch and two internal storage elements:

• • The number of input AND-gates is reduced to 4, because we don't have anything to do when the external input switch is off.

• The output signals are sent to ten lights and back to the internal storage elements.

### 13. Combinational Circuit Logic Gate Diagram

• The number of input AND-gates is reduced to 4, because we don't have anything to do when the external input switch is off.

• The output signals are sent to five lights and back to the internal storage elements:

• ### 14. Master-slave Flip-flop

• • Consider one complete clock cycle:

 Half 1, clock signal is 1: Latch A value is protected. Latch A value is passed to latch B. Latch B value becomes input to the logic circuit. Half 2, clock signal is 0: Latch B value becomes protected. Latch A becomes enabled for writing and accepts the output of the logical circuit.
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### 15. Master-slave Flip-flop, Cont.

• • Master-slave flip-flop a is clock cycle-oriented device and recognizes both 1 and 0 signals:

• Clock signal 1 does B = A and logic circuit input = B.

• Clock signal 0 does A = logic circuit output.

• During 1st phase, when clock=1, previously-computed state becomes current state and is sent to the logic circuit.

• During 2nd phase, when clock=0, next state, computed by logic circuit, is stored in latch A.

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