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A combination of states presents a system behavior.
An FSM consists of five elements:
finite number of states
finite number of external inputs
finite number of external outputs
specification of all possible state transitions
specification of what determines each external output value.
Each transition describes what it takes to get from one state to another.














Implementation of the traffic sign logic is based on the programmable logic array, discussed earlier.
The logic circuit is driven by the inputs from the external switch and two internal storage elements:
The number of input ANDgates is reduced to 4, because we don't have anything to do when the external input switch is off.
The output signals are sent to ten lights and back to the internal storage elements.
The number of input ANDgates is reduced to 4, because we don't have anything to do when the external input switch is off.
The output signals are sent to five lights and back to the internal storage elements:
Consider one complete clock cycle:


Masterslave flipflop a is clock cycleoriented device and recognizes both 1 and 0 signals:
Clock signal 1 does B = A and logic circuit input = B.
Clock signal 0 does A = logic circuit output.
During 1st phase, when clock=1, previouslycomputed state becomes current state and is sent to the logic circuit.
During 2nd phase, when clock=0, next state, computed by logic circuit, is stored in latch A.
Download Digital Works Traffic Sign Macro and try it in simulation mode.
See also: